mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 548

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Memory Map/Register Definition
24.2.4 Read/Write (FB_R/W)
The processor drives the FB_R/W signal to indicate the current bus operation direction. It
is driven high during read bus cycles and low during write bus cycles.
24.2.5 Transfer Start/Address Latch Enable (FB_TS/FB_ALE)
The assertion of FB_TS indicates that the device has begun a bus transaction and the
address and attributes are valid.
In multiplexed mode, an inverted FB_TS (FB_ALE) is available as an address latch
enable, which indicates when the address is being driven on the FB_AD bus.
FB_TS/FB_ALE is asserted for one bus clock cycle.
This device can extend this signal until the first positive clock edge after FB_CSn asserts.
See CSCRn[EXTS] and
24.3 Memory Map/Register Definition
The following tables describe the registers and bit meanings for configuring chip-select
operation.
The actual number of chip selects available depends upon the device and its pin
configuration. If the device does not support certain chip select signals or the pin is not
configured for a chip-select function, then that corresponding set of chip-select registers
has no effect on an external pin.
548
You must set CSMR0[V] before the chip select registers take
effect.
A bus error occurs when writing to reserved register locations.
Extended Transfer Start/Address Latch
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
Note
Enable.
Freescale Semiconductor, Inc.