mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 712

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Memory Map/Register Definition
31.4.6 DAC Control Register 2 (DACx_C2)
Addresses: DAC0_C2 is FFFF_8500h base + 23h offset = FFFF_8523h
712
DACBFMD
DACBFEN
DACBFRP
DACBFUP
Field
Reset
Field
2–1
Read
7–4
3–0
Write
0
Bit
This bitfield controls when the DAC buffer watermark flag will be set. When the DAC buffer read pointer
reaches the word defined by this bitfield, from 1 to 4 words away from the upper limit (DACBUP), the DAC
buffer watermark flag will be set. This allows user configuration of the watermark interrupt.
00
01
10
11
DAC buffer work mode select
00
01
10
11
DAC buffer enable
0
1
DAC buffer read pointer
These 4 bits keep the current value of the buffer read pointer.
DAC buffer upper limit
These 4 bits select the buffer's upper limit. The buffer read pointer cannot exceed it.
7
0
Buffer read pointer disabled. The converted data is always the first word of the buffer.
Buffer read pointer enabled. The converted data is the word that the read pointer points to. It means
converted data can be from any word of the buffer.
1 word
2 words
3 words
4 words
Normal Mode
Swing Mode
One-Time Scan Mode
Reserved
0
6
MCF51JF128 Reference Manual, Rev. 2, 03/2011
DACx_C1 field descriptions (continued)
DACBFRP
DACx_C2 field descriptions
0
5
Preliminary
0
4
Description
Description
1
3
1
2
DACBFUP
Freescale Semiconductor, Inc.
1
1
1
0