mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1298

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Functional Description
protocol. If the target supports the hardware handshake protocol, subsequent commands
are enabled to execute the hardware handshake protocol; otherwise, this command is
ignored by the target.
For additional information about the hardware handshake protocol, refer to
Interface Hardware Handshake Protocol
50.4.1.5.4 BACKGROUND
Provided XCSR[ENBDM] is set (BDM enabled), the BACKGROUND command causes
the target MCU to enter active background (halt) mode as soon as the current CPU
instruction finishes. If ENBDM is cleared (its default value), the BACKGROUND
command is ignored.
A delay of 32 BDC clock cycles is required after the BACKGROUND command to allow
the target MCU to finish its current CPU instruction and enter active background mode
before a new BDC command can be accepted.
After the target MCU is reset into a normal operating mode, the host debugger would
send a WRITE_XCSR_BYTE command to set ENBDM before attempting to send the
BACKGROUND command the first time. Normally, the development host would set
ENBDM once at the beginning of a debug session or after a target system reset, and then
leave the ENBDM bit set during debugging operations. During debugging, the host
would use GO commands to move from active background mode to normal user program
execution and would use BACKGROUND commands or breakpoints to return to active
background mode.
1298
Enter active background mode (if enabled)
host
target
0x04
MCF51JF128 Reference Manual, Rev. 2, 03/2011
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Preliminary
and
Hardware Handshake Abort
Freescale Semiconductor, Inc.
Non-intrusive
Procedure.
Serial