mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1263

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

This table shows the selected PC address capture period as determined by the
XCSR[APCENB], CSR2[APCDIV16], and XCSR[APCSC] fields.
50.3.3 Configuration/Status Register 2 (CSR2)
The 32-bit CSR2 is partitioned into two sections. The upper byte contains status and
configuration bits always accessible to the BDM interface, even if debug mode is
disabled. The lower 24 bits contain fields related to the configuration of the PST trace
buffer (PSTB).
This table summarizes the methods for accessing CSR2.
Freescale Semiconductor, Inc.
READ_CSR2_BYTE
XCSR[APCENB]
APCENB
Field
0
1
1
1
1
1
1
1
1
Table 50-10. PC address capture period (SYNC_PC interval)
Reference method
Automatic PC Synchronization Enable
Enables the periodic output of the PC, which can be used for PST/DDATA trace synchronization
and code profiling.
As described in APCSC, when the enabled periodic timer expires, a SYNC_PC command is sent to
the CPU that generates a forced instruction fetch of the next instruction. The PST/DDATA module
captures the target address as defined by CSR[9] (two bytes if CSR[9] is 0b, three bytes if CSR[9]
is 1b). This produces a PST sequence of the PST marker indicating a 2- or 3-byte address,
followed by the captured instruction address.
0
1
Description
Table 50-9. XCSR Field Descriptions (continued)
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Table 50-11. CSR2 Access Summary
CSR2[APCDIV16]
Disable automatic PC synchronization
Enable automatic PC synchronization
Table continues on the next page...
1
1
1
1
0
0
0
0
Preliminary
Reads bits 31–24 from the BDM interface. Available in all
modes.
XCSR[APCSC]
00
01
10
11
00
01
10
11
Details
128
256
512
1024
2048
4096
8092
16384
SYNC_PC interval (cycles)
Chapter 50 Debug
1263