mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 558

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Functional Description
24.4.6 Mini-FlexBus Timing Examples
24.4.6.1 Basic Read Bus Cycle
During a read cycle, the MCU receives data from memory or a peripheral device. The
following figure shows a read cycle flowchart.
558
State
S1
S2
S3
The timing diagrams throughout this section use signal names
that may not be included on your particular device. Ignore these
extraneous signals.
Also, ignore the AA=0 portions of the diagrams, since this
setting is not supported in the Mini-FlexBus.
Throughout this section:
• FB_D[X] indicates a 16-, or 8-bit wide data bus
• FB_A[Y] indicates an address bus that can be 20 bits wide.
Cycle
Read
Read
All
All
All
Table 24-14. Bus Cycle States (continued)
MCF51JF128 Reference Manual, Rev. 2, 03/2011
FB_TS/FB_ALE is negated on the rising edge of FB_CLK, and FB_CSn is
asserted. Data is driven on FB_AD[X:0] for writes, and FB_AD[X:0] is tristated
for reads. Address continues to be driven on the FB_AD pins that are unused for
data.
Data is driven by the external device before the next rising edge of FB_CLK (the
rising edge that begins S2).
FB_CSn is negated and the internal system bus transfer is completed.
The processor latches data on the rising clock edge entering S2. The external
device can stop driving data after this edge. However, data can be driven until
the end of S3 or any additional address hold cycles.
Address, data, and FB_R/W go invalid off the rising edge of FB_CLK at the
beginning of S3, terminating the read or write cycle.
Description
Preliminary
Note
Note
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