mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1271

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

50.3.6 BDM Address Attribute Register (BAAR)
BAAR defines the address space for memory-referencing BDM commands. BAAR[R,
SZ] are loaded directly from the BDM command, while the lower five bits can be
programmed from the external development system. BAAR is loaded any time AATR is
written and is initialized to a value of 0x05, setting supervisor data as the default address
space. The upper 24 bits of this register are reserved for future use and any attempted
write of these bits is ignored.
Freescale Semiconductor, Inc.
5
6
DRc: 0x05 (BAAR)
R
W
Reset
R
W
Reset
Bit Number
31–8
Field
31
0
15
0
0
0
LLS Mode Exit
VLLSx Modes
Exit
30
0
0
14
0
0
Bit Name
Table 50-18. BDM Address Attribute Register (BAAR)
Reserved for future use by the debug module; must be cleared.
Description
29
0
0
13
0
0
Table 50-17. DBGSR Definition (continued)
MCF51JF128 Reference Manual, Rev. 2, 03/2011
28
0
12
0
0
0
Table 50-19. BAAR Field Descriptions
This bit indicates that an exit from LLS mode has occurred. The debugger loses
communication (including access to this register) while the system is in LLS mode.
When communication is re-established, this bit indicates that the system had been in
LLS mode. The debug modules hold their state during LLS mode, so they do not
require reconfiguration after an exit from LLS mode. The LLS Mode Exit bit is held until
the debugger recognizes that LLS mode was exited. The bit is cleared by a write of 1
to the DBGCR[1] bit (LLS, VLLSx Status Acknowledge bit).
This bit indicates that an exit from one of the VLLSx modes has occurred. The
debugger loses communication (including access to this register) while the system is in
a VLLSx mode. When communication is re-established, this bit indicates that the
system had been in a VLLSx mode. The debug modules lose their state during VLLSx
modes, so they must be reconfigured after an exit from a VLLSx mode. The VLLSx
Mode Exit bit is held until the debugger recognizes that a VLLSx mode was exited. The
bit is cleared by a write of 1 to the DBGCR[1] bit (LLS, VLLSx Status Acknowledge bit).
27
0
0
11
0
0
Table continues on the next page...
26
0
0
10
0
0
25
0
9
0
Preliminary
0
0
24
0
0
8
0
0
23
0
0
7
R
0
Description
22
0
6
0
0
SZ
21
0
0
5
0
20
0
4
0
0
TT
Access: Supervisor write-only
19
0
3
0
0
18
0
0
2
TM
1
Chapter 50 Debug
BDM write-only
17
0
1
0
0
16
0
0
0
1
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