mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 942

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Initialization/Application Information
Once SPTEF is set, it does not clear until it is serviced. SPTEF has an automatic clearing
process which is described in the SPI Status Register (SPIxS) .
38.4.13.4 SPMF
SPMF occurs when the data in the receive data buffer is equal to the data in the SPI
match register. In 8-bit mode, SPMF is set only after bits 7–0 in the receive data buffer
are determined to be equivalent to the value in SPIx_ML. In 16-bit mode, SPMF is set
after bits 15–0 in the receive data buffer are determined to be equivalent to the value in
SPIx_MH:SPIx_ML.
38.4.13.5 TNEAREF
The TNEAREF bit applies when the FIFO feature is supported.
The TNEAREF flag is set when only one 16-bit word or two 8-bit bytes of data remain in
the transmit FIFO provided C3[5] = 0 or when only two 16-bit words or four 8-bit bytes
of data remain in the transmit FIFO provided C3[5] =1. If FIFOMODE is not enabled,
ignore this bit.
Clearing this interrupt depends on the state of C3[3] and the status of TNEAREF. Refer
to the description of the SPI status (S) register.
38.4.13.6 RNFULLF
The RNFULLF bit applies when the FIFO feature is supported.
RNFULLF is set when more than three 16-bit words or six 8-bit bytes of data remain in
the receive FIFO provided C3[4] = 0 or when more than two 16-bit words or four 8-bit
bytes of data remain in the receive FIFO provided C3[4] = 1.
Clearing this interrupt depends on the state of C3[3] and the status of RNFULLF. Refer
to the description of the SPI status (S) register.
38.5 Initialization/Application Information
This section discusses an example of how to initialize and use the SPI.
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
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Freescale Semiconductor, Inc.