mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 774

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Modes of Operation
36.4.1 Wait Mode Operation
During wait mode, the CMT if enabled, will continue to operate normally . However,
there is no change in operating modes of CMT while in wait mode, because the CPU is
not operating.
36.4.2 Stop Mode Operation
This section describes the CMT stop mode operations.
36.4.2.1 Normal Stop Mode Operation
During Normal Stop mode, clocks to the CMT module are halted . No registers are
affected.
Because the clocks are halted, the CMT will resume upon exit from Normal Stop.
Software should ensure that the Normal Stop mode is not entered while the modulator is
still in operation to prevent the CMT_IRO signal from being asserted while in Normal
Stop mode. This may require a time-out period from the time that MSC[MCGEN] bit is
cleared to allow the last modulator cycle to complete.
36.4.2.2 Low Power Stop Mode Operation
During Low Power Stop mode, the CMT module is completely powered off internally
and the CMT_IRO signal state at the time that Low Power Stop mode is entered is
latched and held. To prevent the CMT_IRO signal from being asserted while in Low
Power Stop mode, software should assure that the signal is not active when entering Low
Power Stop mode. Upon wake-up from Low Power Stop mode, the CMT module will be
in the reset state.
774
The assignment of module modes to core modes is chip-
specific. For module-to-core mode assignments, see the chapter
that describes how modules are configured.
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
NOTE
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