mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1197

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

46.3.11 Port Digital Filter Control Register (PCTLx_DFC)
This register contains the control bits to select clock and filter factors for all digital filters
of the port.
Addresses: PCTLB_DFC is FFFF_9210h base + Ah offset = FFFF_921Ah
Freescale Semiconductor, Inc.
PTDFE[7:0]
PTFF[4:0]
Reserved
PTCLKS
Field
Reset
Field
7–0
Read
6–5
4–0
Write
7
Bit
PCTLC_DFC is FFFF_9220h base + Ah offset = FFFF_922Ah
PCTLC_DFC is FFFF_9220h base + Ah offset = FFFF_922Ah
PCTLD_DFC is FFFF_9230h base + Ah offset = FFFF_923Ah
PCTLE_DFC is FFFF_9240h base + Ah offset = FFFF_924Ah
PCTLF_DFC is FFFF_9250h base + Ah offset = FFFF_925Ah
PTCLKS
Only ports B and C have this register.
Digital filter enables
Each PTDFE bit enables the digital filter on the pin when the pin is configured as an input. If the pin is not
configured as an input, the digital filter circuit is not used. When enabled, the digital filter is included in the
signal path to EGPIO and any module that gets control of the pin and configures it as an input.
0
1
Clock select bit
Selects the counting clock for digital filters.
0
1
This read-only bitfield is reserved and always has the value zero.
Filter factor bits
Controls the width of the glitch (in terms of clock cycles) the filter should absorb; glitches less than or
equal to this width setting are not allowed by the filter to pass.
7
0
Digital filter disabled (bypass mode).
Digital filter enabled.
Digital filters count on the bus clock.
Digital filters count on the LPO clock.
0
6
MCF51JF128 Reference Manual, Rev. 2, 03/2011
0
PCTLx_DFE field descriptions
PCTLx_DFC field descriptions
Table continues on the next page...
0
5
Preliminary
NOTE
0
4
Description
Description
0
3
PTFF[4:0]
Chapter 46 Enhanced GPIO (EGPIO)
0
2
0
1
0
0
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