mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 738

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

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Memory Map and Register Definition
33.3.9 DAC Interval Trigger n Control Register (PDBx_DACINTCn)
Addresses: PDB0_DACINTC0 is FFFF_8540h base + 20h offset = FFFF_8560h
33.3.10 DAC Interval n Register (PDBx_DACINTn)
Addresses: PDB0_DACINT0 is FFFF_8540h base + 24h offset = FFFF_8564h
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Bit
Bit
W
W
R
R
Reserved
Reserved
31
31
0
0
31–16
31–2
Field
TOE
Field
EXT
30
30
1
0
0
0
29
29
0
0
28
28
0
0
This read-only bitfield is reserved and always has the value zero.
DAC External Trigger Input Enable
This bit enables the external trigger for DAC interval counter.
0
1
DAC Interval Trigger Enable
This bit enables the DAC interval trigger.
0
1
This read-only bitfield is reserved and always has the value zero.
27
27
0
0
DAC external trigger input disabled. DAC interval counter is reset and started counting when a rising
edge is detected on selected trigger input source or software trigger is selected and SWTRIG is
written with 1.
DAC external trigger input enabled. DAC interval counter is bypassed and DAC external trigger input
triggers the DAC interval trigger.
DAC interval trigger disabled.
DAC interval trigger enabled.
26
26
0
0
25
25
0
0
24
24
0
0
0
MCF51JF128 Reference Manual, Rev. 2, 03/2011
23
23
0
0
PDBx_DACINTCn field descriptions
PDBx_DACINTn field descriptions
22
22
0
0
21
21
0
0
Table continues on the next page...
20
20
0
0
19
19
0
0
18
18
0
0
Preliminary
17
17
0
0
0
16
16
0
0
15
15
0
0
Description
Description
14
14
0
0
13
13
0
0
12
12
0
0
11
11
0
0
10
10
0
0
0
0
9
9
0
0
8
8
INT
Freescale Semiconductor, Inc.
0
0
7
7
0
0
6
6
0
0
5
5
4
0
4
0
0
0
3
3
0
0
2
2
0
0
1
1
0
0
0
0