mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 940

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Functional Description
38.4.11.3 SPI in Stop Mode
Operation in a stop mode where the peripheral bus clock is stopped but internal logic
states are retained depends on the SPI system. The stop mode does not depend on the
SPISWAI bit. Upon entry to this type of stop mode, the SPI module clock is disabled
(held high or low).
The SPI is completely disabled in a stop mode where the peripheral bus clock is stopped
and internal logic states are not retained. After an exit from this type of stop mode, all
registers are reset to their default values, and the SPI module must be re-initialized.
38.4.12 Reset
The reset values of registers and signals are described in
details the registers and their bitfields.
38.4.13 Interrupts
The SPI originates interrupt requests only when the SPI is enabled (the SPE bit in the
SPIx_C1 register is set). The following is a description of how the SPI makes a request
and how the MCU should acknowledge that request. The interrupt vector offset and
interrupt priority are chip dependent.
Four flag bits, three interrupt mask bits, and one interrupt vector are associated with the
SPI system. The SPI interrupt enable mask (SPIE) enables interrupts from the SPI
receiver full flag (SPRF) and mode fault flag (MODF). The SPI transmit interrupt enable
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• If the SPI is in master mode and exchanging data when the CPU enters the stop
• In slave mode, the SPI remains synchronized with the master.
• If a data transmission occurs in slave mode after a reset without a write to
• Reading from SPIx_DH:SPIx_DL after reset always returns zeros.
mode, the transmission is frozen until the CPU exits stop mode. After the exit from
stop mode, data to and from the external SPI is exchanged correctly.
SPIx_DH:SPIx_DL, the transmission consists of "garbage" or the data last received
from the master before the reset.
entered or exited during a transmission. If the slave enters wait
mode in idle mode and exits wait mode in idle mode, neither an
SPRF nor a SPIx_DH:SPIx_DL copy occurs.
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
Register
Definition, which
Freescale Semiconductor, Inc.