mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 234

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Memory Map/Register Description
The supervisor programming model is to be used only by system control software to
implement restricted operating system functions, I/O control, and memory management.
All accesses that affect the control features of ColdFire processors are in the supervisor
programming model, that consists of registers available in user mode as well as the
following control registers:
234
Load: 0x60
Store: 0x40
Load: 0x61
Store: 0x41
Load: 0x62-7
Store: 0x42-7
Load: 0x68-E
Store: 0x48-E
• 16-bit status register (SR)
• 32-bit supervisor stack pointer (SSP)
• 32-bit vector base register (VBR)
• 32-bit CPU configuration register (CPUCR)
command
BDM
• One 16-bit mask register (MASK)
• One 32-bit status register (MACSR) including four indicator bits signaling
Accumulators and extension bytes can be loaded, copied, and stored, and results
from EMAC arithmetic operations generally affect the entire 48-bit destination.
product or accumulation overflow (one for each accumulator: PAV0–PAV3)
1
• Four 32-bit accumulators (ACC0–ACC3)
• Eight 8-bit accumulator extension bytes (two per accumulator). These are
grouped into two 32-bit values for load and store operations (ACCEXT01
and ACCEXT23).
Data register 0 (D0)
see
Data register 1 (D1)
see
Data registers 2-7 (D2-7)
see
Address registers (A0–A6)
Data registers (D0–D7)
Data registers (D0–D7)
Data registers (D0–D7)
Table 11-1. ColdFire core programming model
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Register
Table continues on the next page...
Supervisor/user access registers
2
Preliminary
32
32
32
32
Width
(bits)
R/W
R/W
R/W
R/W
Access
See
Exception
See
Exception
POR: Undefined
Else: Unaffected
POR: Undefined
Else: Unaffected
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Reset value
Reset
Reset
No
No
No
No
MOVEC
Written
with
3