mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 939

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

38.4.11.1 SPI in Run Mode
In run mode with the SPI system enable (SPE) bit in the SPI control register clear, the
SPI system is in a low-power, disabled state. SPI registers can still be accessed, but
clocks to the core of this module are disabled .
38.4.11.2 SPI in Wait Mode
SPI operation in wait mode depends upon the state of the SPISWAI bit in SPI Control
Register 2.
Freescale Semiconductor, Inc.
• If SPISWAI is clear, the SPI operates normally when the CPU is in wait mode.
• If SPISWAI is set, SPI clock generation ceases and the SPI module enters a power
conservation state when the CPU is in wait mode.
• If SPISWAI is set and the SPI is configured for master, any transmission and
• If SPISWAI is set and the SPI is configured as a slave, any transmission and
reception in progress stops at wait mode entry. The transmission and reception
resumes when the SPI exits wait mode.
reception in progress continues if the SPSCK continues to be driven from the
master. This keeps the slave synchronized to the master and the SPSCK.
If the master transmits data while the slave is in wait mode, the slave continues
to send data consistent with the operation mode at the start of wait mode (that is,
if the slave is currently sending its SPIx_DH:SPIx_DL to the master, it continues
to send the same byte. Otherwise, if the slave is currently sending the last data
received byte from the master, it continues to send each previously received data
from the master byte).
Care must be taken when expecting data from a master while
the slave is in a wait mode or a stop mode where the peripheral
bus clock is stopped but internal logic states are retained. Even
though the shift register continues to operate, the rest of the SPI
is shut down (that is, an SPRF interrupt is not generated until an
exit from stop or wait mode). Also, the data from the shift
register is not copied into the SPIx_DH:SPIx_DL registers until
after the slave SPI has exited wait or stop mode. An SPRF flag
and SPIx_DH:SPIx_DL copy is only generated if wait mode is
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
Note
Chapter 38 Serial Peripheral Interface (SPI)
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