mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 252

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Processor Exceptions
until all previous operations, including all pending write operations, are complete. If any
previous write terminates with an access error, it is guaranteed to be reported on the NOP
instruction.
11.3.3.2 Address Error Exception
The default operation of the V1 ColdFire processor is the generation of an illegal address
reset event if an address error is detected. If CPUCR[ARD] equals 1, then the reset is
disabled and a processor exception is generated as detailed below.
Any attempted execution transferring control to an odd instruction address (if bit 0 of the
target address is set) results in an address error exception.
Any attempted use of a word-sized index register (Xn.w) or a scale factor of eight on an
indexed effective addressing mode generates an address error, as does an attempted
execution of a full-format indexed addressing mode, which is defined by bit 8 of
extension word 1 being set.
If an address error occurs on an RTS instruction, the Version 1 ColdFire processor
overwrites the faulting return PC with the address error stack frame.
11.3.3.3 Illegal Instruction Exception
The default operation of the V1 ColdFire processor is the generation of an illegal opcode
reset event if an illegal instruction is detected. If CPUCR[IRD] is set, the reset is disabled
and a processor exception is generated as detailed below. There is one special case
involving the ILLEGAL opcode (0x4AFC); attempted execution of this instruction
always generates an illegal instruction exception, regardless of the state of the
CPUCR[IRD] bit.
The ColdFire variable-length instruction set architecture supports three instruction sizes:
16, 32, or 48 bits. The first instruction word is known as the operation word (or opword),
while the optional words are known as extension word 1 and extension word 2. The
opword is further subdivided into three sections: the upper four bits segment the entire
ISA into 16 instruction lines, the next 6 bits define the operation mode (opmode), and the
low-order 6 bits define the effective address. The opword line definition is shown below.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Line
OpMode
Effective Address
Mode
Register
Figure 11-3. ColdFire Instruction Operation Word (Opword) Format
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
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