mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 818

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Memory Map and Register Definition
37.3.14 Features Mode Selection (FTMx_MODE)
This register contains the control bits used to configure the fault interrupt and fault
control, capture test mode, PWM synchronization, write protection, channel output
initialization, and enable the enhanced features of the FTM. These controls relate to all
channels within this module.
Addresses: FTM0_MODE is FFFF_8440h base + 20h offset = FFFF_8460h
818
FAULTIE
FAULTM
CH0F
Field
Reset
Field
Read
6–5
Write
0
7
Bit
FTM1_MODE is FFFF_8480h base + 20h offset = FFFF_84A0h
FAULTIE
0
1
Channel 0 Flag
See the register description.
0
1
Fault Interrupt Enable
Enables the generation of an interrupt when a fault is detected by FTM and the FTM fault control is
enabled.
0
1
Fault Control Mode
Defines the FTM fault control mode.
FAULTM is write protected, these bits can only be written if MODE[WPDIS] = 1.
00
01
10
11
7
0
No channel event has occurred.
A channel event has occurred.
No channel event has occurred.
A channel event has occurred.
Fault control interrupt is disabled.
Fault control interrupt is enabled.
Fault control is disabled for all channels.
Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is
the manual fault clearing.
Fault control is enabled for all channels, and the selected mode is the manual fault clearing.
Fault control is enabled for all channels, and the selected mode is the automatic fault clearing.
FTMx_STATUS field descriptions (continued)
0
6
MCF51JF128 Reference Manual, Rev. 2, 03/2011
FAULTM
FTMx_MODE field descriptions
Table continues on the next page...
0
5
Preliminary
CAPTEST
0
4
Description
Description
PWMSYNC
0
3
WPDIS
1
2
Freescale Semiconductor, Inc.
INIT
0
1
FTMEN
0
0