mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1071

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

43.3.6 UART Status Register 2 (UARTx_S2)
The S2 register provides inputs to the MCU for generation of UART interrupts or DMA
requests. Also, this register can be polled by the MCU to check the status of these bits.
This register can be read or written at any time, with the exception of the MSBF and
RXINV bits which should only be changed by the user between transmit and receive
packets.
Addresses: UART0_S2 is FFFF_8140h base + 5h offset = FFFF_8145h
Freescale Semiconductor, Inc.
RXEDGIF
LBKDIF
MSBF
Field
Reset
Field
Read
Write
7
6
5
Bit
UART1_S2 is FFFF_8160h base + 5h offset = FFFF_8165h
LBKDIF
0
1
LIN Break Detect Interrupt Flag
LBKDIF is set when LBKDE is set and a LIN break character is detected, when 11 consecutive logic 0s (if
C1[M] = 0) or 12 consecutive logic 0s (if C1[M] = 1) appear on the receiver input. LBKDIF is set right after
receiving the last LIN break character bit. LBKDIF is cleared by writing a 1 to it.
0
1
RxD Pin Active Edge Interrupt Flag
RXEDGIF is set when an active edge (falling if RXINV = 0, rising if RXINV=1) on the RxD pin occurs.
RXEDGIF is cleared by writing a 1 to it. See
NOTE: The active edge is only detected when in two wire mode and on receive data coming from the
0
1
Most Significant Bit First
Setting this bit reverses the order of the bits that are transmitted and received on the wire. This bit does
not affect the polarity of the bits, the location of the parity bit or the location of the start or stop bits.This bit
7
0
No parity error has been detected since the last time this flag was cleared. If the receive buffer has a
depth greater than 1 then there may be data in the receive buffer what was received with a parity
error.
At least one dataword was received with a parity error since the last time this flag was cleared.
No LIN break character has been detected.
LIN break character has been detected.
No active edge on the receive pin has occurred.
An active edge on the receive pin has occurred.
RxD pin.
RXEDGIF
UARTx_S1 field descriptions (continued)
0
6
MCF51JF128 Reference Manual, Rev. 2, 03/2011
UARTx_S2 field descriptions
Table continues on the next page...
MSBF
0
5
Chapter 43 Universal Asynchronous Receiver/Transmitter (UART)
Preliminary
RXINV
0
4
RXEDGIF description
Description
Description
RWUID
0
3
for additional details.
BRK13
0
2
LBKDE
0
1
RAF
0
0
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