mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 916

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Register Definition
Addresses: SPI0_S is FFFF_81A0h base + 3h offset = FFFF_81A3h, SPI1_S is FFFF_81B0h base + 3h offset = FFFF_81B3h
916
• The RNFULLF and TNEAREF help improve the efficiency of FIFO operation when
• The RNFULLF can generate an interrupt if the RNFULLIEN bit in the C3 register is
• The TNEAREF can generate an interrupt if the TNEARIEN bit in the C3 register is
transfering large amounts of data. These flags provide a "watermark" feature of the
FIFOs to allow continuous transmissions of data when running at high speed.
set, which allows the CPU to start emptying the receive FIFO without delaying the
reception of subsequent bytes. The user can also determine if all data in the receive
FIFO has been read by monitoring the RFIFOEF.
set, which allows the CPU to start filling the transmit FIFO before it is empty and
thus to prevent breaks in SPI transmission.
SPRF
Reset
Field
Read
Write
7
Bit
At an initial POR, the values of TNEAREF and RFIFOEF are
0. However, the status (S) register and both TX and RX FIFOs
are reset due to a change of SPIMODE, FIFOMODE or SPE. If
this type of reset occurs and FIFOMODE is 0, TNEAREF and
RFIFOEF continue to reset to 0. If this type of reset occurs and
FIFOMODE is 1, TNEAREF and RFIFOEF reset to 1.
SPRF
SPI read buffer full flag (when FIFO is not supported or not enabled) or SPI read FIFO FULL flag (when
FIFO is supported and enabled)
When the FIFO is not supported or not enabled (FIFOMODE is not present or is 0): This bit enables the
interrupt for SPI receive buffer full (SPRF) and mode fault (MODF) events.
When the FIFO is supported and enabled (FIFOMODE is 1): This bit enables the SPI to interrupt the CPU
when the receive FIFO is full. An interrupt occurs when the SPRF bit is set or the MODF bit is set.
When the FIFO is not supported or not enabled (FIFOMODE is not present or is 0): SPRF is set at the
completion of an SPI transfer to indicate that received data may be read from the SPI data (DH:DL)
register. When the receive DMA request is disabled (RXDMAE is 0), SPRF is cleared by reading SPRF
while it is set and then reading the SPI data register. When the receive DMA request is enabled
(RXDMAE is 1), SPRF is automatically cleared when the DMA transfer for the receive DMA request is
completed (RX DMA Done is asserted).
When FIFOMODE is 1: This bit indicates the status of the read FIFO when FIFOMODE is enabled. The
SPRF is set when the read FIFO has received 64 bits (4 words or 8 bytes) of data from the shifter and
there have been no CPU reads of the SPI data (DH:DL) register. When the receive DMA request is
disabled (RXDMAE is 0), SPRF is cleared by reading the SPI data register, which empties the FIFO
7
0
SPMF
0
6
MCF51JF128 Reference Manual, Rev. 2, 03/2011
SPI0_S field descriptions
Table continues on the next page...
SPTEF
1
5
Preliminary
NOTE
MODF
0
4
Description
RNFULLF
0
3
TNEAREF
0
2
Freescale Semiconductor, Inc.
TXFULLF
0
1
RFIFOEF
0
0