mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 428

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Functional Description
428
• The SARn is loaded with the source (read) address. If the transfer is from a
• The DARn is initialized with the destination (write) address. If the transfer is from a
• SARn and DARn change after each data transfer depending on DCRn[SSIZE,
• BCRn[BCR] must be loaded with the total number of bytes to be transferred. It is
• As soon as the channel has been initialized, it may be started by setting
• Programming the channel for a software-initiated request causes the channel to
• The hardware can automatically clear DCRn[ERQ], disabling the peripheral request,
• Changes to DCRn are effective immediately while the channel is active. To avoid
peripheral device to memory, the source address is the location of the peripheral data
register. If the transfer is from memory to a peripheral device or memory, the source
address is the starting address of the data block. This can be any appropriately-
aligned address.
peripheral device to memory, or from memory to memory, the DARn is loaded with
the starting address of the data block to be written. If the transfer is from memory to
a peripheral device, DARn is loaded with the address of the peripheral data register.
This address can be any appropriately-aligned address.
DSIZE, SINC, DINC, SMOD, DMOD] and the starting addresses. Increment values
can be 1, 2, 4 for byte, word, or longword transfers, respectively. If the address
register is programmed to remain unchanged, the register is not incremented after the
data transfer.
decremented by 1, 2, or 4 at the end of each transfer, depending on the transfer size.
DSRn[DONE] must be cleared for channel startup.
DCRn[START] or a properly-selected peripheral DMA request, depending on the
status of DCRn[ERQ]. For a software-initiated transfer, the channel can be started by
setting DCRn[START] as part of a single 32-bit write to the last longword of the
TCDn, that is, it is not required to write the DCRn with START cleared and then
perform a second write to explicitly set START.
request the system bus and start transferring data immediately. If the channel is
programmed for peripheral-initiated request, a properly-selected peripheral DMA
request must be asserted before the channel begins the system bus transfers.
when BCRn reaches zero by setting DCRn[D_REQ].
problems with changing a DMA channel setup, write a one to DSRn[DONE] to stop
the DMA channel.
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
Freescale Semiconductor, Inc.