mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1050

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Functional Description
The ARBL bit must be cleared (by software) by writing 1 to it.
42.4.6.5 Timeout Interrupt in SMBus
When the IICIE bit is set, the I2C module asserts a timeout interrupt (outputs SLTF and
SHTF2) upon detection of any of the mentioned timeout conditions, with one exception.
The SCL high and SDA high TIMEOUT mechanism must not be used to influence the
timeout interrupt output, because this timeout indicates an idle condition on the bus.
SHTF1 rises when it matches the SCL high and SDA high TIMEOUT and falls
automatically just to indicate the bus status. The SHTF2's timeout period is the same as
that of SHTF1, which is short compared to that of SLTF, so another control bit,
SHTF2IE, is added to enable or disable it.
42.4.7 Programmable Input Glitch Filter
An I2C glitch filter has been added outside legacy I2C modules but within the I2C
package. This filter can absorb glitches on the I2C clock and data lines for the I2C
module. The width of the glitch to absorb can be specified in terms of the number of
(half) bus clock cycles. A single Programmable Input Glitch Filter control register is
provided. Effectively, any down-up-down or up-down-up transition on the data line that
occurs within the number of clock cycles programmed in this register is ignored by the
I2C module. The programmer must only specify the size of the glitch (in terms of bus
clock cycles) for the filter to absorb and not pass.
SCL, SDA
Noise
internal signals
suppress
circuits
SCL, SDA
external signals
DFF
DFF
DFF
DFF
Figure 42-65. Programmable input glitch filter diagram
42.4.8 Address Matching Wakeup
When a primary, range, or general call address match occurs when the I2C module is in
slave receive mode, the MCU wakes from low power mode with no peripheral bus
running. After the address matching IAAS bit is set, an interrupt is sent at the end of
address matching to wake the core. The IAAS bit must be cleared after the clock
recovery.
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
1050
Freescale Semiconductor, Inc.