mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 769

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Chapter 35 Low Power Timer (LPTMR)
The LPTMR counter register is reset when the LPTMR is disabled or if the counter
register overflows. If the CSR[TFC] control bit is set then the LPTMR counter register is
also reset whenever the CSR[TCF] status flag is set.
The LPTMR counter register continues incrementing when the core is halted in debug
mode.
The LPTMR counter register cannot be initialized, but can be read at any time. On each
read of the LPTMR counter register, software must first write to the LPTMR counter
register with any value. This will synchronize and register the current value of the
LPTMR counter register into a temporary register. The contents of the temporary register
are returned on each read of the LPTMR counter register.
When reading the LPTMR counter register, the bus clock must be at least two times
faster than the rate at which the LPTMR counter is incrementing, otherwise incorrect data
may be returned.
35.4.6 LPTMR hardware trigger
The LPTMR hardware trigger asserts at the same time the timer compare flag is set and
can be used to trigger hardware events in other peripherals without software intervention.
The hardware trigger is always enabled.
When the LPTMR compare register is set to zero with the free running counter bit clear,
the LPTMR hardware trigger will assert on the first compare and does not negate. When
the LPTMR compare register is set to a non-zero value (or if the free running counter bit
is set) the LPTMR hardware trigger will assert on each compare and negate on the
following increment of the LPTMR counter register.
35.4.7 LPTMR interrupt
The LPTMR interrupt is generated whenever the CSR[TIE] and CSR[TCF] are set. The
CSR[TCF] is cleared by disabling the LPTMR or by writing a logic one to it.
The CSR[TIE] can be altered and the CSR[TCF] can be cleared while the LPTMR is
enabled.
The LPTMR interrupt is generated asynchronously to the system clock and can be used to
generate a wakeup from any low power mode, including the low leakage modes
(provided the LPTMR is enabled as a wakeup source).
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
Freescale Semiconductor, Inc.
769