mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 944

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Initialization/Application Information
944
SPIx_C2 = 0xC0(%11000000)
SPIx_BR = 0x00(%00000000)
SPIx_S = 0x00(%00000000)
SPIx_MH = 0xXX
SPIx_ML = 0xXX
SPIx_DH = 0xxx
SPIx_DL = 0xxx
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6:4
Bit 3:0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3:0
Bit 3:0
In 16-bit mode, this register holds bits 8–15 of the hardware match buffer. In 8-bit mode, writes to this register
will be ignored.
Holds bits 0–7 of the hardware match buffer.
In 16-bit mode, this register holds bits 8–15 of the data to be transmitted by the transmit buffer and received by
the receive buffer.
Holds bits 0–7 of the data to be transmitted by the transmit buffer and received by the receive buffer.
SPMIE
SPIMODE
TXDMAE
MODFEN
BIDIROE
RXDMAE
SPISWAI
SPC0
SPRF
SPMF
SPTEF
MODF
RNFULLF,
TNEARF,
TXFULLF, and
RFIFOEF
MCF51JF128 Reference Manual, Rev. 2, 03/2011
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Preliminary
1
1
0
0
0
0
0
0
0
000
000
0
0
0
0
0
0
0
SPI hardware match interrupt enabled
Configures SPI for 16-bit mode
DMA request disabled
Disables mode fault function
SPI data I/O pin acts as input
DMA request disabled
SPI clocks operate in wait mode
uses separate pins for data input and output
Reserved
Sets prescale divisor to 1
Sets baud rate divisor to 2
Flag is set when receive data buffer is full
Flag is set when SPIMH/L = receive data buffer
Flag is set when transmit data buffer is empty
Mode fault flag for master mode
Reserved (when FIFOMODE is not present or is 0) or FIFO
flags (when FIFOMODE is 1)
FIFOMODE is not enabled
Freescale Semiconductor, Inc.