mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 172

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Module Operation in Low Power Modes
1. Using the LLWU module, the external pins available for this MCU do not require the associated peripheral function to be
2. For the RAM3 size on a particular device, refer to
3. In VLPR mode, FlexRAM enabled as EEPROM is not writable (writes are ignored) but can be read. There are no access
4. FlexRAM is always powered off in VLLSx modes.
5. Before executing an entry to VLPR mode, the MCG must be in one of two of its operating modes, each with a particular
6. The CMP in stop or VLPS mode supports high speed or low speed, external pin-to-pin or external pin-to-DAC compares.
7. The CMP in LLS or VLLSx mode supports only low speed, external pin-to-pin or external pin-to-DAC compares.
8. The SPISWAI bit must be cleared for master mode operation in wait modes.
9. Use an externally generated bit clock or an externally generated audio master clock (including EXTAL).
10. TSI wakeup from LLS and VLLSx modes is limited to a single selectable pin.
172
12-bit DAC
FTM
MTIM
PDB
LPTMR
CMT
UART
SPI
I
USB FS/LS
USB DCD
I
EGPIO
RGPIO
TSI
IRQ
2
2
C
S/SAI
enabled. The only requirement is for the function controlling the pin (GPIO or peripheral) to be configured as an input to
allow a transition to occur to the LLWU.
restrictions in VLPR mode for FlexRAM configured as traditional RAM.
clock source selected:
Windowed, sampled, and filtered modes of operation are not available in stop, VLPS, LLS, or VLLSx modes.
Windowed, sampled, and filtered modes of operation are not available in stop, VLPS, LLS, or VLLSx modes.
Module
• Either the MCG must be in its BLPE operating mode with only the low gain oscillator selected, or
• The MCG must be in its BLPI operating mode with only the 2 MHz IRC selected.
FF with external
Table 7-2. Module operation in low power modes (continued)
Static, address
Static, wakeup
match wakeup
on edge
Wakeup
Wakeup
Wakeup
clock
STOP
Static
Static
Static
Static
Static
Static
Static
Static
Static
FF
9
MCF51JF128 Reference Manual, Rev. 2, 03/2011
master mode,
Maximum 2
500 kbps in
250 kbps in
slave mode
125 kbps
50 kbps
VLPR
Static
Mbps
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
Human-machine interface (HMI)
Communication interfaces
RAM
master mode,
Preliminary
slave mode
500 kbps in
250 kbps in
Maximum 2
125 kbps
50 kbps
sizes.
Timers
VLPW
Static
Mbps
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
8
Static, wakeup
Static, address
match wakeup
Maximum 2
on edge
Wakeup
Wakeup
Wakeup
Mbps
VLPS
Static
Static
Static
Static
Static
Static
Static
Static
Static
FF
9
Static, pins
Static, pins
Wakeup
latched
latched
Freescale Semiconductor, Inc.
Static
Static
Static
Static
Static
Static
Static
Static
Static
Static
Static
Static
LLS
FF
10
Wakeup
OFF, pins
OFF, pins
latched
latched
VLLSx
Static
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
FF
10