mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1112

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Functional description
43.4.2.8.2 Fast data tolerance
The following figure shows how much a fast received frame can be misaligned. The fast
stop bit ends at RT10 instead of RT16 but is still sampled at RT8, RT9, and RT10.
For an 8-bit data character, data sampling of the stop bit takes the receiver 154 RT cycles
(9 bit times × 16 RT cycles + 10 RT cycles).
With the misaligned character shown in the above figure, the receiver counts 154 RT
cycles at the point when the count of the transmitting device is 160 RT cycles (10 bit
times × 16 RT cycles).
The maximum percent difference between the receiver count and the transmitter count of
a fast 8-bit character with no errors is:
For a 9-bit data character, data sampling of the stop bit takes the receiver 170 RT cycles
(10 bit times × 16 RT cycles + 10 RT cycles).
With the misaligned character shown in the above figure, the receiver counts 170 RT
cycles at the point when the count of the transmitting device is 176 RT cycles (11 bit
times × 16 RT cycles).
The maximum percent difference between the receiver count and the transmitter count of
a fast 9-bit character with no errors is:
43.4.2.9 Receiver wakeup
The C1[WAKE] bit determines how the UART is brought out of the standby state to
process an incoming message. The C1[WAKE] bit enables either idle line wakeup or
address mark wakeup.
Receiver wakeup is not supported when C7816[ISO_7816E] is set/enabled since multi-
receiver systems are not allowed.
1112
((154 − 160) ÷ 154) × 100 = 3.90%
((170 − 176) ÷ 170) × 100 = 3.53%
RECEIVER
RT CLOCK
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Figure 43-103. Fast data
STOP
Preliminary
SAMPLES
DATA
IDLE OR NEXT FRAME
Freescale Semiconductor, Inc.