mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1265

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor, Inc.
COPHR
BFHBR
PSTBH
IOPHR
IADHR
BDFR
Field
29
28
27
26
25
24
23
Computer Operating Properly Halt After Reset
Specifies operation of the device after a COP reset. This bit is 0b after a power-on reset and is
unaffected by any other reset.
NOTE: This bit can be changed only if XCSR[ENBDM] is 1b and the system is not secure.
0
1
Illegal Operation Halt After Reset
Specifies operation of the device after an illegal operation reset. This bit is 0b after a power-on
reset and is unaffected by any other reset.
NOTE: This bit can be changed only if XCSR[ENBDM] is 1b and the flash is not secure.
0
1
Illegal Address Halt After Reset
Specifies operation of the device after an illegal address reset. This bit is 0b after a power-on reset
and is unaffected by any other reset.
NOTE: This bit can be changed only if XCSR[ENBDM] is 1b and the system is not secure.
0
1
Reserved. Must write 0.
BDM Force Halt on BDM Reset
Specifies operation of the device after a BDM reset (on any reset based on external BKGD logic
implementation). This bit is cleared after a power-on reset and is unaffected by any other reset.
NOTE: This bit can be changed only if XCSR[ENBDM] is 1b and the system is not secure.
0
1
Background Debug Force Reset
Forces a BDM reset to the device. This bit always reads as 0 after the reset has been initiated.
0
1
PST Trace Buffer Halt
Indicates if the processor is halted due to the PST trace buffer being full when recording in
obtrusive mode.
0
1
Description
Table 50-12. CSR2 Field Descriptions (continued)
MCF51JF128 Reference Manual, Rev. 2, 03/2011
The device immediately enters normal operation mode.
The device halts (as if the BKGD pin was held low after a power-on reset).
The device immediately enters normal operation mode.
The device halts (as if the BKGD pin was held low after a power-on reset).
The device immediately enters normal operation mode.
The device halts (as if the BKGD pin was held low after a power-on reset).
The device immediately enters normal operation mode.
The device halts (as if the BKGD pin was held low after a power-on reset).
No reset
Force a BDM reset
Not halted
Halted
Table continues on the next page...
Preliminary
Chapter 50 Debug
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