mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1069

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor, Inc.
TDRE
RDRF
IDLE
Field
TC
7
6
5
4
Transmit Data Register Empty Flag
TDRE will set when the number of datawords in the transmit buffer (D and C3[T8])is equal to or less than
the number indicated by TWFIFO[TXWATER]. A character that is in the process of being transmitted is
not included in the count. To clear TDRE, read S1 when TDRE is set and then write to the UART data
register (D). For more efficient interrupt servicing all data except the final value to be written to the buffer
should written to D/C3[T8]. Then S1 can be read before writing the final data value, resulting in the
clearing of the TRDE flag. This is more efficient since the TDRE will reassert until the watermark has been
exceeded so attempting to clear the TDRE every write will be ineffective until sufficient data has been
written.
0
1
Transmit Complete Flag
TC is cleared when there is a transmission in progress or when a preamble or break character is loaded.
TC is set when the transmit buffer is empty and no data, preamble, or break character is being
transmitted. When TC is set, the transmit data output signal becomes idle (logic 1). When 7816E is set/
enabled this bit is set after any NACK signal has been received but prior to any corresponding guard
times expiring. TC is cleared by reading S1 with TC set and then doing one of the following:
0
1
Receive Data Register Full Flag
RDRF is set when the number of datawords in the receive buffer is equal to or more than the number
indicated by TWFIFO[TXWATER]. A dataword that is in the process of being received is not included in
the count. RDRF is prevented from setting while S2[LBKDE] is set. Additionally, when S2[LBKDE] is set,
datawords that are received will be stored in the receive buffer but will over-write each other. To clear
RDRF, read S1 when RDRF is set and then read the UART data register (D). For more efficient interrupt
and DMA operation all data except the final value is to be read from the buffer using D/C3[T8]/ED. The S1
should then be read and the final data value read, resulting in the clearing of the RDRF flag. Even if the
RDRF flag is set, data will continue to be received until an overrun condition occurs.
0
1
Idle Line Flag
IDLE is set when 10 consecutive logic 1s (if C1[M] = 0), 11 consecutive logic 1s (if C1[M] = 1 and C4[M10]
= 0), or 12 consecutive logic 1s (if C1[M] = 1, C4[M10] = 1, and C1[PE] = 1) appear on the receiver input.
After the IDLE flag is cleared, a frame must be received (although not necessarily stored in the data
buffer, for example if C2[RWU] is set) or a LIN break character must set the S2[LBKDIF] flag before an
idle condition can set the IDLE flag. To clear IDLE, read UART status S1 with IDLE set and then read D.
Idle detection is not supported when 7816E is set/enabled and hence this flag is ignored.
NOTE: When the receiver wakeup bit (RWU) is set and WAKE is cleared, an idle line condition sets the
• Writing to the UART data register (D) to transmit new data
• Queuing a preamble by clearing and then setting the C2[TE] bit.
• Queuing a break character by writing 1 to SBK in C2
The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER].
The amount of data in the transmit buffer is less than or equal to the value indicated by
TWFIFO[TXWATER] at some point in time since the flag has been cleared.
Transmitter active (sending data, a preamble, or a break).
Transmitter idle (transmission activity complete).
The number of datawords in the receive buffer is less than the number indicated by RXWATER.
The number of datawords in the receive buffer is equal to or greater than the number indicated by
RXWATER at some point in time since this flag was last cleared.
IDLE flag if RWUID is set, else the IDLE flag does not get set.
MCF51JF128 Reference Manual, Rev. 2, 03/2011
UARTx_S1 field descriptions
Table continues on the next page...
Chapter 43 Universal Asynchronous Receiver/Transmitter (UART)
Preliminary
Description
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