mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 968

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Memory Map/Register Definitions
39.4.11 Error Interrupt Status Register (USBx_ERRSTAT)
The Error Interrupt Status Register contains enable bits for each of the error sources
within the USB Module. Each of these bits are qualified with their respective error enable
bits. All bits of this Register are logically OR'd together and the result placed in the
ERROR bit of the ISTAT register. After an interrupt bit has been set it may only be
cleared by writing a one to the respective interrupt bit. Each bit is set as soon as the error
conditions is detected. Therefore, the interrupt does not typically correspond with the end
of a token being processed. This register contains the value of 0x00 after a reset.
Addresses: USB0_ERRSTAT is FFFF_9000h base + 88h offset = FFFF_9088h
968
CRC5EOF
DMAERR
Reserved
BTSERR
BTOERR
CRC16
DFN8
Reset
Field
Read
Write
7
6
5
4
3
2
1
Bit
BTSERR
w1c
This bit is set when a bit stuff error is detected. If set, the corresponding packet is rejected due to the
error.
This read-only bit is reserved and always has the value zero.
This bit is set if the USB Module has requested a DMA access to read a new BDT but has not been given
the bus before it needs to receive or transmit data. If processing a TX transfer this would cause a transmit
data underflow condition. If processing a RX transfer this would cause a receive data overflow condition.
This interrupt is useful when developing device arbitration hardware for the microprocessor and the USB
Module to minimize bus request and bus grant latency. This bit is also set if a data packet to or from the
host is larger than the buffer size allocated in the BDT. In this case the data packet is truncated as it is put
into buffer memory.
This bit is set when a bus turnaround timeout error occurs. The USB Module contains a bus turnaround
timer that keeps track of the amount of time elapsed between the token and data phases of a SETUP or
OUT TOKEN or the data and handshake phases of a IN TOKEN. If more than 16 bit times are counted
from the previous EOP before a transition from IDLE, a bus turnaround timeout error occurs.
This bit is set if the data field received was not 8 bits in length. USB Specification 1.0 requires that data
fields be an integral number of bytes. If the data field was not an integral number of bytes, this bit is set.
This bit is set when a data packet is rejected due to a CRC16 error.
This error interrupt has two functions. When the USB Module is operating in peripheral mode
(HOSTMODEEN=0), this interrupt detects CRC5 errors in the token packets generated by the host. If set
the token packet was rejected due to a CRC5 error.
When the USB Module is operating in host mode (HOSTMODEEN=1), this interrupt detects End Of
Frame (EOF) error conditions. This occurs when the USB Module is transmitting or receiving data and the
SOF counter reaches zero. This interrupt is useful when developing USB packet scheduling software to
ensure that no USB transactions cross the start of the next frame.
7
0
0
0
6
MCF51JF128 Reference Manual, Rev. 2, 03/2011
USBx_ERRSTAT field descriptions
DMAERR
Table continues on the next page...
w1c
0
5
Preliminary
BTOERR
w1c
0
4
Description
DFN8
w1c
0
3
CRC16
w1c
0
2
Freescale Semiconductor, Inc.
CRC5EOF
w1c
0
1
PIDERR
w1c
0
0