mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 395

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

While in VLPR mode, the regulator is slow responding and cannot manage fast load
transitions. Therefore, do not change the clock frequency. In addition, do not modify the
clock source or BDIV in the MCG module, the module clock enables in the SIM, or any
clock divider registers.
To re-enter normal run mode, simply clear RUNM. The PMSTAT register is a read-only
status register that can be used to determine when the system has completed an exit to
RUN mode. When PMSTAT=RUN, the system is in run regulation mode and the MCU
can run at full speed in any clock mode. If a higher execution frequency is desired, poll
the PMSTAT register until it is set to RUN when returning from VLPR mode.
VLPR mode also provides the option to return to run regulation if any interrupt occurs.
Implement this option by setting the low power wakeup on interrupt (LPWUI) bit in the
PMCTRL register. Any reset always causes an exit from VLPR and returns the device
run mode after the MCU exits its reset flow. The RUNM bits are cleared by hardware on
any interrupt when LPWUI is set or on any reset.
17.4.3.3 BDM in Run and VLPR Mode
If the MCU is unsecure and BDM mode is enabled, then the MCU can be fully debugged
using the BDM in RUN and VLPR modes. If XCSR[ENBDM] = 0, before entering
active BDM mode, the host must write XCSR[ENBDM] = 1 before sending a
BACKGROUND command.
17.4.4 Wait Modes
This device contains two different wait modes:
17.4.4.1 WAIT Mode
WAIT mode is entered by executing a STOP instruction after configuring the device
appropriately. Upon execution of the STOP instruction, the CPU enters a low-power state
in which it is not clocked.
Freescale Semiconductor, Inc.
• Wait
• Very low power wait (VLPW)
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
Chapter 17 System Mode Controller (SMC)
395