mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 686

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Memory Map/Register Definitions
30.7.5 DAC Control Register (CMPx_DACCR)
Addresses: CMP0_DACCR is FFFF_8530h base + 4h offset = FFFF_8534h
686
DACEN
VRSEL
VOSEL
COUT
Field
Reset
Field
Read
5–0
Write
0
7
6
Bit
DACEN
NOTE: Edge detection during Stop mode is only supported on platforms that allow peripherals to be
0
1
Analog Comparator Output
Reading the COUT bit will return the current value of the analog comparator output. The register bit is
reset to zero and will read as CR1[INV] when the Analog Comparator module is disabled (CR1[EN] = 0).
Writes to this bit are ignored.
DAC Enable
This bit is used to enable the DAC. When the DAC is disabled, it is powered down to conserve power.
0
1
Supply Voltage Reference Source Select
0
1
DAC Output Voltage Select
This bit selects an output voltage from one of 64 distinct levels.
DACO = (Vin/64) * (VOSEL[5:0] + 1), so the DACO range is from Vin/64 to Vin.
7
0
Falling edge on COUT has not been detected.
Falling edge on COUT has occurred.
DAC is disabled.
DAC is enabled.
Vin1 is selected as resistor ladder network supply reference Vin.
Vin2 is selected as resistor ladder network supply reference Vin.
clocked during Stop modes. If the CFF flag is active during Stop mode, then SMELB must be set
to 0 for cases where it is not receiving a clock during Stop mode.
VRSEL
CMPx_SCR field descriptions (continued)
0
6
MCF51JF128 Reference Manual, Rev. 2, 03/2011
CMPx_DACCR field descriptions
0
5
Preliminary
0
4
Description
Description
0
3
VOSEL
0
2
Freescale Semiconductor, Inc.
0
1
0
0