mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 739

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Reset
Reset
33.3.11 Pulse-Out n Enable Register (PDBx_POnEN)
Addresses: PDB0_PO0EN is FFFF_8540h base + 28h offset = FFFF_8568h
33.3.12 Pulse-Out n Delay Register (PDBx_POnDLY)
Addresses: PDB0_PO0DLY is FFFF_8540h base + 2Ch offset = FFFF_856Ch
Freescale Semiconductor, Inc.
Bit
Bit
W
W
R
R
Reserved
31
31
0
0
POEN
31–16
DLY1
15–0
31–8
Field
Field
Field
INT
7–0
30
30
0
0
29
29
0
0
28
28
0
0
DAC Interval
These bits specify the interval value for DAC interval trigger. DAC interval trigger triggers DAC[1:0] update
when the DAC interval counter is equal to the DACINT. Reading these bits returns the value of internal
register that is effective for the current PDB cycle.
This read-only bitfield is reserved and always has the value zero.
PDB Pulse-Out Enable
These bits enable the pulse output. Only lower Y bits are implemented in this MCU.
0
1
PDB Pulse-Out Delay 1
27
27
0
0
PDB Pulse-Out disabled
PDB Pulse-Out enabled
26
26
0
0
25
25
0
0
PDBx_DACINTn field descriptions (continued)
24
24
DLY1
0
0
MCF51JF128 Reference Manual, Rev. 2, 03/2011
23
23
0
0
22
22
PDBx_POnDLY field descriptions
0
0
PDBx_POnEN field descriptions
21
21
0
0
Table continues on the next page...
20
20
0
0
0
19
19
0
0
18
18
0
0
Preliminary
17
17
0
0
16
16
0
0
15
15
0
0
Description
Description
Description
14
14
0
0
13
13
0
0
12
12
0
0
Chapter 33 Programmable Delay Block (PDB)
11
11
0
0
10
10
0
0
0
0
9
9
DLY2
0
0
8
8
0
0
7
7
0
0
6
6
0
0
5
5
POEN
4
0
4
0
0
0
3
3
0
0
2
2
0
0
1
1
739
0
0
0
0