mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1181

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

45.6.2 Application 2: 16-bit Message Transmission using SPI
In this second example, a 16-bit message is transmitted using three programmable output
pins. The output pins include a serial clock, an active-high chip select, and the serial data
bit. The software is configured to sample the serial data bit at the rising-edge of the clock
with the data sent in a most-significant to least-significant bit order. The resulting 3-bit
output is shown in the following figure.
For this example, the processing of the SPI message is considerably more complex than
the generation of a simple square wave of the previous example. The code snippet used to
extract the data bit from the message and build the required GPIO data register writes is
shown in the following example.
# subtest: send a 16-bit message via a SPI interface using a RGPIO
00510: 4fef fff4
00514: 48d7 008c
00518: 3439 0080 0582
0051e: 760f
00520: 7e10
00522: 207c 00c0 0003
00528: 203c 0000 ffff
0052e: 3140 fffd
00532: 3140 0001
00536: 223c 0001 0000
0053c: 2001
0053e: e6a8
00540: 5880
00542: 1080
00544: 6002
00548: 3202
0054a: 2001
0054c: e6a8
0054e: 1080
00550: 5880
00552: e38a
00554: 51fc
00556: 51fc
00558: 51fc
0055a: 51fc
0055c: 1080
0055e: 5387
00560: 66e6
Freescale Semiconductor, Inc.
gpio_data
gpio_clk
gpio_cs
Protocol
Figure 45-10. GPIO SPI Example Timing Diagram
# the SPI protocol uses a 3-bit value: clock, chip-select, data
# the data is centered around the rising-edge of the clock
send_16b_spi_message_rgpio:
L%1:
MCF51JF128 Reference Manual, Rev. 2, 03/2011
align
lea
movm.l
mov.w
movq.l
movq.l
mov.l
mov.l
mov.w
mov.w
mov.l
mov.l
lsr.l
addq.l
mov.b
bra.b
align
mov.w
mov.l
lsr.l
mov.b
addq.l
lsl.l
tpf
tpf
tpf
tpf
mov.b
subq.l
bne.b
15
16
-12(%sp),%sp
&0x8c,(%sp)
RAM_BASE+message2,%d2
&15,%d3
&16,%d7
&RGPIO_DATA+1,%a0
&0xffff,%d0
%d0,-3(%a0)
%d0,1(%a0)
&0x10000,%d1
%d1,%d0
%d3,%d0
&4,%d0
%d0,(%a0)
L%1
4
%d2,%d1
%d1,%d0
%d3,%d0
%d0,(%a0)
&4,%d0
&1,%d2
%d0,(%a0)
&1,%d7
L%1
Preliminary
14
13
# allocate stack space
# save d2,d3,d7
# static shift count
# message bit length
# pointer to low-order data byte
# data value for _ENB and _DIR regs
# set RGPIO_DIR register
# set RGPIO_ENB register
# d1[17:16] = {clk, cs}
# copy into temp reg
# align in d0[2:0]
# set clk = 1
# initialize data
# d1[17:15] = {clk, cs, data}
# copy into temp reg
# align in d0[2:0]
# transmit data with clk = 0
# force clk = 1
# d2[15] = new message data bit
# preserve 50% duty cycle
# transmit data with clk = 1
# decrement loop counter
2
# get 16-bit message
Chapter 45 Rapid GPIO (RGPIO)
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