mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 414

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Memory Map and Registers
Any operation involving a DMA channel follows the same three steps:
19.3
Descriptions of each register and its bit assignments follow. Modifying DMA control
registers during a transfer can result in undefined operation. The following table shows
the mapping of DMA controller registers. The DMA programming model is accessed via
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1. Channel initialization—The transfer control descriptor, contained in the channel
2. Data transfer—The DMA accepts requests for data transfers. Upon receipt of a
3. Channel termination—Occurs after the operation is finished successfully or due to an
• Dual-address transfers—A dual-address transfer consists of a read followed by a
write and is initiated by a request using the DCRn[START] bit or by a peripheral
DMA request. The read data is temporarily held in the DMA channel hardware until
the write operation. Two types of single transfers occur: a read from a source address
followed by a write to a destination address. See the following figure.
registers, is loaded with address pointers, a byte-transfer count, and control
information using accesses from the slave peripheral bus.
request, it provides address and bus control for the transfers via its master connection
to the system bus and temporary storage for the read data. The channel performs one
or more source read and destination write data transfers.
error. The channel indicates the operation status in the channel's DSR, described in
the definitions of the DMA Status Registers (DSRn) and Byte Count Registers
(BCRn).
Memory Map and Registers
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Figure 19-2. Dual-Address Transfer
DMA
Control and Data
Control and Data
Preliminary
Write
Read
Peripheral
Peripheral
Memory/
Memory/
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