mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 420

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Reset
Memory Map and Registers
19.3.3 Destination Address Register (DMA_DARn)
Addresses: DMA_DAR0 is FFFF_E400h base + 104h offset = FFFF_E504h
19.3.4 DMA Status Register / Byte Count Register (DMA_DSR_BCRn)
DSR and BCR are two logical registers that occupy one 32-bit address. DSRn occupies
bits 31–24, and BCRn occupies bits 23–0. DSRn contains flags indicating the channel
status, and BCRn contains the number of bytes yet to be transferred for a given block.
On the successful completion of the write transfer, BCRn decrements by 1, 2, or 4 for
byte, word, or longword accesses, respectively. BCRn is cleared if a 1 is written to
DSR[DONE].
In response to an event, the DMA controller writes to the appropriate DSRn bit. Only a
write to DSRn[DONE] results in action. DSRn[DONE] is set when the block transfer is
complete.
When a transfer sequence is initiated and BCRn[BCR] is not a multiple of 4 or 2 when
the DMA is configured for longword or word transfers, respectively, DSRn[CE] is set
and no transfer occurs.
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Bit
W
R
31
0
31–0
Field
DAR
30
0
DMA_DAR1 is FFFF_E400h base + 114h offset = FFFF_E514h
DMA_DAR2 is FFFF_E400h base + 124h offset = FFFF_E524h
DMA_DAR3 is FFFF_E400h base + 134h offset = FFFF_E534h
29
0
28
0
Each DAR contains the byte address used by the DMA controller to write data. The DARn is typically
aligned on a 0-modulo-dsize boundary—that is, on the natural alignment of the destination data. Because
the system only supports 24-bit addresses, DARn[31:24] is ignored.
27
0
26
0
25
0
24
0
MCF51JF128 Reference Manual, Rev. 2, 03/2011
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22
0
DMA_DARn field descriptions
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0
20
0
19
0
18
0
Preliminary
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0
16
0
DAR
15
0
Description
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0
13
0
12
0
11
0
10
0
0
9
0
8
Freescale Semiconductor, Inc.
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7
0
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0
5
4
0
0
3
0
2
0
1
0
0