mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 349

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

15.4.7 Clear Interrupt Mask Register (INTC_CIMR)
The INTC_SIMR register provides a simple memory-mapped mechanism to set a given
bit in the INTC_IMR{H,L} registers to disable (mask) a given interrupt request. The data
value on a register write causes the corresponding bit in the INTC_IMR{H,L} registers to
be set. Setting INTC_SIMR[SALL] forces the entire contents of INTC_IMR{H,L}
registers to set, masking all interrupts. Attempting to read this register generates an error
termination.
IMR[63:44] are reserved for future use, so writes using these data values are ignored.
This register is provided so interrupt service routines can easily mask the given interrupt
request without the need to perform a read-modify-write sequence on the
INTC_IMR{H,L} registers.
Address: INTC_CIMR is FFFF_FFC0h base + 1Dh offset = FFFF_FFDDh
15.4.8 INTC Set Interrupt Force Register (INTC_SFRC)
The INTC_SFRC register provides a simple memory-mapped mechanism to set a given
bit in the INTC_FRC register to assert a specific level interrupt request. The data value
written causes the appropriate bit in the INTC_FRC register to be set. Attempted reads of
this register generate an error termination.
Freescale Semiconductor, Inc.
Reserved
CIMR
CALL
Reset
Field
Read
5–0
Write
7
6
Bit
Reserved
This bit is reserved.
Clear all
Clear all bits in the INTC_IMR{H,L} register, enabling all interrupt requests.
0
1
Clear the corresponding bit in the INTC_IMR{H,L} registers, enabling the interrupt request.
7
0
Set only those bits specified in the CIMR field.
Clear all bits in INTC_IMR{H,L} register. The CIMR field is ignored.
CALL
0
6
MCF51JF128 Reference Manual, Rev. 2, 03/2011
INTC_CIMR field descriptions
0
5
Preliminary
0
4
Description
0
3
CIMR
Chapter 15 Interrupt Controller (INTC)
0
2
0
1
0
0
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