mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 381

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mcf51jf128

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mcf51jf128
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Mcf51jf128 Reference Manual
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Chapter 17
System Mode Controller (SMC)
17.1 Introduction
The System Mode Controller (SMC) is responsible for sequencing the system into and
out of all low power stop and run modes. Specifically, it monitors events to trigger
transitions between power modes while controlling the power, clocks and memories of
the system to achieve the power consumption and functionality of that mode.
This chapter describes all the available low power modes, the sequence followed to enter/
exit each mode and the functionality available while in each of the modes.
The SMC is able to function during even the deepest low power modes.
17.2 Modes of Operation
The V1 ColdFire CPU has two primary modes of operation: run and stop. The STOP
instruction is used to invoke both stop and wait modes. The CPU does not differentiate
between stop and wait modes.
In addition, Freescale MCUs also augment stop, wait, and run modes in a number of
ways. The power management controller (PMC) contains a run and a stop mode
regulator. Run regulation is used in normal run, wait and stop modes. Stop mode
regulation is used during all very low power and low leakage modes. During stop mode
regulation the bus frequencies are limited for the very low power modes.
The SMC provides the user with multiple power options. The very low power run
(VLPR) mode can drastically reduce run time power when maximum bus frequency is
not required to handle the application needs. From normal run mode, the run mode
(RUNM) bit field can be modified to change the the MCU into VLPR mode when limited
frequency is sufficient for the application. From VLPR mode, a corresponding wait
(VLPW) and stop (VLPS) mode can be entered.
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
Freescale Semiconductor, Inc.
381

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