mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1068

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Module Memory Map
43.3.5 UART Status Register 1 (UARTx_S1)
The S1 register provides inputs to the MCU for generation of UART interrupts or DMA
requests. This register can also be polled by the MCU to check the status of these bits. To
clear a flag, the status register should be read followed by a read or write (depending on
interrupt flag type) to the UART Data Register. Other instructions can be executed
between the two steps as long as it does not compromise the handling of I/O, but the
order of operations is important for flag clearing. When a flag is configured to trigger a
DMA request, assertion of the associated DMA done signal from the DMA controller,
clears the flag.
Addresses: UART0_S1 is FFFF_8140h base + 4h offset = FFFF_8144h
1068
Field
Reset
Read
Write
Bit
UART1_S1 is FFFF_8160h base + 4h offset = FFFF_8164h
If the condition that results in the assertion of the flag, interrupt
or DMA request is not resolved prior to clearing the flag, the
flag (and interrupt/DMA request) will reassert. For example, if
the DMA or interrupt service routine failed to write sufficient
data to the transmit buffer to raise it above the watermark level,
the flag will reassert and generate another interrupt or DMA
request.
Reading an empty data register to clear one of these flags
causes the FIFO pointers to get out of alignment. A receive
FIFO flush reinitializes the pointers.
TDRE
0
1
7
1
Normal transmitter operation.
Queue break character(s) to be sent.
TC
UARTx_C2 field descriptions (continued)
1
6
MCF51JF128 Reference Manual, Rev. 2, 03/2011
RDRF
0
5
Preliminary
NOTE
NOTE
IDLE
0
4
Description
OR
0
3
NF
0
2
Freescale Semiconductor, Inc.
FE
0
1
PF
0
0