mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 557

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

24.4.5.1 Data Transfer Cycle States
An on-chip state machine controls the data-transfer operation in the device. The
following figure shows the state-transition diagram for basic read and write cycles.
The following table describes the states as they appear in subsequent timing diagrams.
Freescale Semiconductor, Inc.
1. S0: At the first clock edge, the address, attributes, and FB_TS/FB_ALE are driven.
2. S1: FB_CSn is asserted at the second rising clock edge to indicate the device
3. S2: Read data is sampled on the third clock edge. After this edge read data can be tri-
4. S3: FB_CSn is negated at the fourth rising clock edge. This last clock of the bus
State
S0
selected; by that time, the address and attributes are valid and stable. FB_TS/
FB_ALE is negated at this edge.
For a write transfer, data is driven on the bus at this clock edge and continues to be
driven until one clock cycle after FB_CSn negates. For a read transfer, data is also
driven into the device during this cycle.
stated.
cycle uses what would be an idle clock between cycles to provide hold time for
address, attributes, and write data.
Figure 24-13. Data-Transfer-State-Transition Diagram
Cycle
All
Next Cycle
MCF51JF128 Reference Manual, Rev. 2, 03/2011
S3
Table 24-14. Bus Cycle States
The read or write cycle is initiated. On the rising clock edge, the device places a
valid address on FB_ADn, asserts FB_TS/FB_ALE, and drives FB_R/W high for
a read and low for a write.
Description
Table continues on the next page...
Preliminary
Wait States
S0
S2
Chapter 24 External Bus Interface (Mini-FlexBus)
S1
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