mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 681

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

30.7 Memory Map/Register Definitions
Address offsets are in terms of bytes for the ColdFire V1 architecture.
The ColdFire V1 IP Bus interface is designed such that a single 16-bit access by the
MCU is serialized into two 8-bit accesses onto the bus. Similarly, a single 32-bit access
by the MCU is serialized into four 8-bit accesses onto the bus. The register order defined
above is such that a single 32-bit access by the ColdFire MCU could (in this order):
Freescale Semiconductor, Inc.
FFFF_8530
FFFF_8531
FFFF_8532
FFFF_8533
FFFF_8534
FFFF_8535
1. Initialize the mux and delay block settings
2. Configure and enable the analog comparator
3. Configure filtering
4. Clear edge detection status and enable interrupts
Absolute
• If enabled, the Filter Block will incur up to 1 bus clock additional latency penalty on
• CR1[WE] and CR1[SE] are mutually exclusive.
address
(hex)
COUT due to the fact that COUT (which is crossing clock domain boundaries) must
be resynchronized to the bus clock.
• If CR1[SE] = 1, the external SAMPLE input is used as sampling clock
• IF CR1[SE] = 0, the divided bus clock is used as sampling clock
CMP Control Register 0 (CMP0_CR0)
CMP Control Register 1 (CMP0_CR1)
CMP Filter Period Register (CMP0_FPR)
CMP Status and Control Register (CMP0_SCR)
DAC Control Register (CMP0_DACCR)
MUX Control Register (CMP0_MUXCR)
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Register name
CMPx memory map
Preliminary
(in bits)
Width
8
8
8
8
8
8
Access
R/W
R/W
R/W
R/W
R/W
R/W
Chapter 30 Comparator (CMP)
Reset value
00h
00h
00h
00h
00h
00h
Section/
30.7.1/
30.7.2/
30.7.3/
30.7.4/
30.7.5/
30.7.6/
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