mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 911

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

38.3.1 SPI control register 1 (SPIx_C1)
This read/write register includes the SPI enable control, interrupt enables, and
configuration options.
Addresses: SPI0_C1 is FFFF_81A0h base + 0h offset = FFFF_81A0h, SPI1_C1 is FFFF_81B0h base + 0h offset = FFFF_81B0h
Freescale Semiconductor, Inc.
FFFF_81B6
FFFF_81B7
FFFF_81B8
FFFF_81B9
Absolute
address
(hex)
SPTIE
SPIE
Reset
Field
SPE
Read
Write
7
6
5
Bit
SPI match register high (SPI1_MH)
SPI match register low (SPI1_ML)
Reserved
Reserved
SPIE
SPI interrupt enable: for SPRF and MODF (when FIFO is not supported or not enabled) or for read FIFO
(when FIFO is supported and enabled)
When the FIFO is not supported or not enabled (FIFOMODE is not present or is 0): This bit enables the
interrupt for SPI receive buffer full (SPRF) and mode fault (MODF) events.
When the FIFO is supported and enabled (FIFOMODE is 1): This bit enables the SPI to interrupt the CPU
when the receive FIFO is full. An interrupt occurs when the SPRF bit is set or the MODF bit is set.
0
1
SPI system enable
This bit enables the SPI system and dedicates the SPI port pins to SPI system functions. If SPE is
cleared, the SPI is disabled and forced into an idle state, and all status bits in the S register are reset.
0
1
SPI transmit interrupt enable
7
0
Interrupts from SPRF and MODF are inhibited—use polling (when FIFOMODE is not present or is 0)
or Read FIFO Full Interrupts are disabled (when FIFOMODE is 1)
Request a hardware interrupt when SPRF or MODF is 1 (when FIFOMODE is not present or is 0) or
Read FIFO Full Interrupts are enabled (when FIFOMODE is 1)
SPI system inactive
SPI system enabled
SPE
0
6
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Register name
SPIx memory map (continued)
SPI0_C1 field descriptions
Table continues on the next page...
SPTIE
0
5
Preliminary
MSTR
0
4
Description
CPOL
0
3
(in bits)
Width
Chapter 38 Serial Peripheral Interface (SPI)
8
8
CPHA
Access
R/W
R/W
1
2
Reset value
SSOE
00h
00h
0
1
Section/
38.3.10/
LSBFE
38.3.7/
38.3.8/
38.3.9/
page
920
920
921
923
0
0
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