mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 923

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

38.3.10 SPI clear interrupt register (SPIx_CI)
This register applies only for an instance of the SPI module that supports the FIFO
feature.
The register has four bits dedicated to clearing the interrupts. Writing 1 to these bits
clears the corresponding interrupts if the INTCLR bit in the C3 register is 1. Reading
these bits always returns 0.
This register also has two read-only bits to indicate the transmit FIFO and receive FIFO
overrun conditions. When the receive FIFO is full and data is received, RXFOF is set.
Similarily, when the transmit FIFO is full and a write to the data register occurs, TXFOF
is set. These flags are cleared when the CI register is read while the flags are set.
The register has two more read-only bits to indicate the error flags. These flags are set
when, due to some spurious reason, entries in the FIFO become greater than 8. At this
point, all the flags in the status register are reset, and entries in the FIFO are flushed with
the corresponding error flags set. These flags are cleared when the CI register is read
while the flags are set.
Addresses: SPI0_CI is FFFF_81A0h base + 9h offset = FFFF_81A9h
Freescale Semiconductor, Inc.
TXFERR
Field
Reset
Field
Read
Write
7
Bit
TXFERR
This bit enables the SPI to use a 64-bit FIFO (8 bytes or four 16-bit words) for both transmit and receive
buffers.
0
1
Transmit FIFO error flag
This flag indicates that a transmit FIFO error occurred because entries in the FIFO exceed 8.
0
1
7
0
Buffer mode disabled
Data available in the receive data buffer
No transmit FIFO error occurred
A transmit FIFO error occurred
RXFERR
0
6
MCF51JF128 Reference Manual, Rev. 2, 03/2011
SPI0_C3 field descriptions (continued)
SPI0_CI field descriptions
Table continues on the next page...
TXFOF
0
5
Preliminary
RXFOF
0
4
Description
Description
TNEAREFCI
0
0
3
Chapter 38 Serial Peripheral Interface (SPI)
RNFULLFCI
0
2
0
SPTEFCI
0
0
1
SPRFCI
0
0
0
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