mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1145

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Reset
44.3.4 SAI Transmit Configuration 3 Register (I2Sx_TCR3)
This register cannot be altered when the transmit enable bit is set.
Addresses: I2S0_TCR3 is FFFF_8200h base + Ch offset = FFFF_820Ch
Freescale Semiconductor, Inc.
Bit
W
R
Reserved
Reserved
31
0
WDFL
31–17
15–4
Field
Field
TCE
3–0
16
30
0
29
0
28
0
Divides down the audio master clock to generate the bit clock when configured for an internal bit clock.
The division value is (DIV + 1) * 2.
This read-only bitfield is reserved and always has the value zero.
Transmit channel enable
Enables a data channel for a transmit operation. A channel must be enabled before its FIFO can be
accessed.
0
1
This read-only bitfield is reserved and always has the value zero.
Word flag configuration
Configures which word the start of word flag is set. The value written should be one less than the word
number (for example, write zero to configure for the first word in the frame). When configured to a value
greater than the Frame Size field, then the start of word flag is never set.
27
0
Transmit data channel is disabled.
Transmit data channel is enabled.
26
0
25
0
24
0
0
I2Sx_TCR2 field descriptions (continued)
MCF51JF128 Reference Manual, Rev. 2, 03/2011
23
0
22
0
Chapter 44 Integrated Interchip Sound (I2S) / Synchronous Audio Interface (SAI)
I2Sx_TCR3 field descriptions
21
0
20
0
19
0
18
0
Preliminary
17
0
16
0
15
0
Description
Description
14
0
13
0
12
0
11
0
10
0
0
0
9
0
8
0
7
0
6
0
5
4
0
0
3
WDFL
0
2
0
1
1145
0
0