mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1098

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Functional description
Hardware supports odd or even parity. When parity is enabled, the bit immediately
preceding the stop bit is the parity bit.
When the transmit shift register is not transmitting a frame, the transmit data output
signal goes to the idle condition, logic 1. If at any time software clears the C2[TE] bit, the
transmitter enable signal goes low and the transmit signal goes idle.
If software clears C2[TE] while a transmission is in progress, the character in the transmit
shift register continues to shift out, provided S1[TC] flag was cleared during the data
write sequence. To clear the S1[TC] flag, the S1 register must be read followed by a write
to UARTx_D register.
If the S1[TC] flag is cleared during character transmission and the C2[TE] bit is cleared,
the transmission enable signal is deasserted at the completion of current frame. Following
this, the transmit data out signal enters the idle state even if there is data pending in the
UART transmit data buffer. To ensure that all the data written in the FIFO is transmitted
on the link before clearing C2[TE], wait for the S1[TC] flag to set. Alternatively, the
same can be achieved by setting TWFIFO[TXWATER] to 0x0 and waiting for
S1[TDRE] to set.
43.4.1.4 Transmitting break characters
Setting the C2[SBK] loads the transmit shift register with a break character. A break
character contains all logic 0s and has no start, stop, or parity bit. Break character length
depends on the C1[M] and C1[PE] bits, the S2[BRK13] bit, and the C4[M10] bit. Refer
to the following table.
As long as C2[SBK] is set, transmitter logic continuously loads break characters into the
transmit shift register. After software clears the C2[SBK] bit, the shift register finishes
transmitting the last break character and then transmits at least one logic 1. The automatic
logic 1 at the end of a break character guarantees the recognition of the start bit of the
next character. Break bits are not supported when C7816[ISO_7816E] is set/enabled.
1098
S2[BRK13]
0
0
0
0
1
1
Table 43-96. Transmit break character length
MCF51JF128 Reference Manual, Rev. 2, 03/2011
C1[M]
0
1
1
1
0
1
Preliminary
C4[M10]
—
—
—
0
1
1
C1[PE]
—
—
—
—
0
1
Freescale Semiconductor, Inc.
Bits transmitted
10
11
11
12
13
14