mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1175

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

45.3.3 RGPIO Data Register (RGPIO_DATA)
The read/write RGPIO_DATA register specifies the write data for a properly-enabled
RGPIO output pin or the sampled read data value for a properly-enabled input pin. An
attempted read of the RGPIO_DATA register returns undefined data for disabled pins
because the data value depends on the chip-level pin muxing and pad implementation. At
reset, all bits in the RGPIO_DATA registers are cleared.
To set bits in the RGPIO_DATA register, directly set the RGPIO_DATA bits or set the
corresponding bits in the RGPIO_SET register. To clear bits in the RGPIO_DATA
register, directly clear the RGPIO_DATA bits or clear the corresponding bits in the
RGPIO_CLR register. Setting a bit in the RGPIO_TOG register inverts (toggles) the state
of the corresponding bit in the RGPIO_DATA register.
Address: RGPIO_DATA is C00000h base + 2h offset = 00C0_0002h
45.3.4 RGPIO Pin Enable Register (RGPIO_ENB)
The read/write RGPIO_ENB register configures the corresponding package pin as an
RGPIO pin instead of the normal GPIO pin mapped onto the peripheral bus.
Freescale Semiconductor, Inc.
Reset
Read
Write
Bit
DATA
15–0
15–0
Field
Field
DIR
15
0
14
0
Data direction
0
1
RGPIO data
0
1
A properly-enabled RGPIO pin is configured as an input.
A properly-enabled RGPIO pin is configured as an output.
A properly-enabled RGPIO output pin is driven with a logic 0, or a properly-enabled RGPIO input pin
was read as a logic 0.
A properly-enabled RGPIO output pin is driven with a logic 1, or a properly-enabled RGPIO input pin
was read as a logic 1.
13
0
12
0
MCF51JF128 Reference Manual, Rev. 2, 03/2011
11
0
RGPIO_DATA field descriptions
RGPIO_DIR field descriptions
10
0
0
9
Preliminary
0
8
DATA
Description
Description
0
7
0
6
0
5
Chapter 45 Rapid GPIO (RGPIO)
0
4
0
3
0
2
0
1
1175
0
0