mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 261

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

This section includes the assumptions concerning the timing values and the execution
time details.
11.3.4.1 Timing Assumptions
For the timing data presented in this section, these assumptions apply:
Freescale Semiconductor, Inc.
1. The OEP is loaded with the opword and all required extension words at the
2. The OEP does not experience any sequence-related pipeline stalls. The most
3. The OEP completes all memory accesses without any stall conditions caused by the
4. All operand data accesses are aligned on the same byte boundary as the operand size;
• C is the number of processor clock cycles, including all applicable operand fetches
• R/W is the number of operand reads (R) and writes (W) required by the instruction.
and writes, and all internal core cycles required to complete the instruction execution.
An operation performing a read-modify-write function is denoted as (1/1).
beginning of each instruction execution. This implies that the OEP does not wait for
the IFP to supply opwords and/or extension words.
common example of stall involves consecutive store operations, excluding the
MOVEM instruction. For all STORE operations (except MOVEM), certain hardware
resources within the processor are marked as busy for two clock cycles after the final
decode and select/operand fetch cycle (DSOC) of the store instruction. If a
subsequent STORE instruction is encountered within this 2-cycle window, it is
stalled until the resource again becomes available. Thus, the maximum pipeline stall
involving consecutive STORE operations is two cycles. The MOVEM instruction
uses a different set of resources and this stall does not apply.
memory itself. Thus, the timing details provided in this section assume that an
infinite zero-wait state memory is attached to the processor core.
for example, 16-bit operands aligned on 0-modulo-2 addresses, 32-bit operands
aligned on 0-modulo-4 addresses.
The processor core decomposes misaligned operand references into a series of
aligned accesses as shown in
address[1:0]
01 or 11
Table 11-23. Misaligned Operand References
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Table continues on the next page...
Table
Word
Size
11-23.
Preliminary
Bus Operations
Byte, Byte
Additional C(R/W)
1(0/1) if write
2(1/0) if read
Chapter 11 Core
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