mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 240

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Memory Map/Register Description
11.2.6 Vector base register (VBR)
The VBR contains the base address of the exception vector table in the memory. To
access the vector table, the displacement of an exception vector is added to the value in
VBR. The lower 20 bits of the VBR are not implemented by ColdFire processors. They
are assumed to be zero, forcing the table to be aligned on a 1 MB boundary.
In addition, because the V1 ColdFire core supports a 16 MB address space, the upper
byte of the VBR is also forced to zero. The VBR can be used to relocate the exception
vector table from its default position in the flash memory (address 0x(00)00_0000) to the
base of the RAM (address 0x(00)80_0000) if needed.
11.2.7 CPU configuration register (CPUCR)
This register provides supervisor mode configurability of specific core functionality.
Particular hardware features can be enabled/disabled individually based on the state of
the CPUCR.
240
Reset
Reset
BDM:
W
W
R
R
31
15
0
0
–
–
Program the Flash Memory Controller's configuration and
control settings only while the Flash Memory Controller is idle.
Changing settings while a flash access is in progress can lead to
non-deterministic behavior.
System software is required to maintain memory coherence
when any segment of the program flash memory cache is
programmed. For example, all buffer data associated with the
30
14
0
0
–
–
29
13
0
0
–
–
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Table 11-8. Vector base register (VBR)
28
12
0
0
–
–
27
11
0
0
–
–
Store: 0xC1 (VBR)
Load: 0xE1 (VBR)
0x801 (VBR)
26
10
0
0
–
–
Preliminary
25
NOTE
NOTE
0
0
9
–
–
24
0
0
8
–
–
23
–
0
7
–
Base Address
22
0
6
–
–
21
0
5
–
–
20
0
4
–
–
Freescale Semiconductor, Inc.
Access: Supervisor read/
19
–
–
3
–
–
BDM read/write
18
–
–
2
–
–
write
17
–
–
1
–
–
16
–
–
0
–
–