mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 832

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Memory Map and Register Definition
832
FAULTF2
FAULTF1
FAULTF0
Field
2
1
0
Clear FAULTF by reading the FMS register while FAULTFn is set and then writing a 0 to FAULTFn
FAULTF while there is no existing fault condition at the fault input n. Writing a 1 to FAULTFn has no
effect. FAULTFn bit is also cleared when FAULTF bit is cleared.
If another fault condition is detected at fault input n before the clearing sequence is completed, the
sequence is reset so FAULTFn remains set after the clearing sequence is completed for the earlier fault
condition.
0
1
Fault Detection Flag 2
Set by hardware when fault control is enabled, the corresponding fault input is enabled and a fault
condition is detected in the fault input.
Clear FAULTF by reading the FMS register while FAULTFn is set and then writing a 0 to FAULTFn
FAULTF while there is no existing fault condition at the fault input n. Writing a 1 to FAULTFn has no
effect. FAULTFn bit is also cleared when FAULTF bit is cleared.
If another fault condition is detected at fault input n before the clearing sequence is completed, the
sequence is reset so FAULTFn remains set after the clearing sequence is completed for the earlier fault
condition.
0
1
Fault Detection Flag 1
Set by hardware when fault control is enabled, the corresponding fault input is enabled and a fault
condition is detected in the fault input.
Clear FAULTF by reading the FMS register while FAULTFn is set and then writing a 0 to FAULTFn
FAULTF while there is no existing fault condition at the fault input n. Writing a 1 to FAULTFn has no
effect. FAULTFn bit is also cleared when FAULTF bit is cleared.
If another fault condition is detected at fault input n before the clearing sequence is completed, the
sequence is reset so FAULTFn remains set after the clearing sequence is completed for the earlier fault
condition.
0
1
Fault Detection Flag 0
Set by hardware when fault control is enabled, the corresponding fault input is enabled and a fault
condition is detected in the fault input.
Clear FAULTF by reading the FMS register while FAULTFn is set and then writing a 0 to FAULTFn
FAULTF while there is no existing fault condition at the fault input n. Writing a 1 to FAULTFn has no
effect. FAULTFn bit is also cleared when FAULTF bit is cleared.
If another fault condition is detected at fault input n before the clearing sequence is completed, the
sequence is reset so FAULTFn remains set after the clearing sequence is completed for the earlier fault
condition.
0
1
No fault condition was detected in the fault input.
A fault condition was detected in the fault input.
No fault condition was detected in the fault input.
A fault condition was detected in the fault input.
No fault condition was detected in the fault input.
A fault condition was detected in the fault input.
No fault condition was detected in the fault input.
A fault condition was detected in the fault input.
FTMx_FMS field descriptions (continued)
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
Description
Freescale Semiconductor, Inc.