mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 339

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Reset
Each bit of the IMR[n] is associated with a corresponding bit of the interrupt request
input vector. The equations defining this association are:
For Vectors 64-102, n=Vector_Number - 64, else for Vectors 110-114, n = Vector_Number - 71
Therefore, vector 64 corresponds to n = 0, vector 65 to n = 1, etc., vector 113 to n = 42,
and vector 114 to n = 43.
Each peripheral request input is first qualified by the contents of the IMR registers before
it is used elsewhere in the interrupt controller, that is:
qualified_interrupt_request[n] = interrupt_request_input[n] + ~INTC_IMR[n]
Since this interrupt controller supports 44 request inputs, the upper 20 bits of the
INTC_IMRH are reserved for future use. Writes to these bits are ignored and reads return
zeroes.
The contents of the IMR do not affect the operation of the software settable force
interrupt registers.
Address: INTC_IMRH is FFFF_FFC0h base + 8h offset = FFFF_FFC8h
Freescale Semiconductor, Inc.
Bit
W
R
Reserved
31
0
IMR43
IMR42
IMR41
31–12
Field
11
10
30
9
0
29
0
28
0
Because this register and the corresponding low register
together represent 64 bits, this register's bits are actually
numbered 63-32 (not 31-0).
This read-only bitfield is reserved and always has the value zero.
Interrupt mask register 43
0
1
Interrupt mask register 42
0
1
Interrupt mask register 41
27
0
The interrupt request is enabled.
The interrupt request is disabled.
The interrupt request is enabled.
The interrupt request is disabled.
26
0
25
0
24
0
MCF51JF128 Reference Manual, Rev. 2, 03/2011
23
0
22
0
0
INTC_IMRH field descriptions
21
0
Table continues on the next page...
20
0
19
0
18
0
Preliminary
NOTE
17
0
16
0
15
0
Description
14
0
13
0
12
0
11
0
10
0
Chapter 15 Interrupt Controller (INTC)
0
9
0
8
0
7
0
6
0
5
4
0
0
3
0
2
0
1
339
0
0