mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 863

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Chapter 37 FlexTimer (FTM)
system clock
write 1 to TRIG0 bit
TRIG0 bit
trigger_0 input
synchronized trigger_0
by system clock
trigger 0 event
Notes
- All hardware trigger (input signals: trigger_0, trigger_1, and trigger_2) have this same behavior
Figure 37-180. Hardware Trigger Event
37.4.11.2 Software Trigger
A software trigger event occurs when 1 is written to the SWSYNC bit. The SWSYNC bit
is cleared when 0 is written to it or when the PWM synchronization (initiated by the
software event) is completed.
If the software trigger event occurs together with the event that clears the SWSYNC bit,
then the synchronization is made using this trigger event and the SWSYNC bit remains
set because of the last write.
For example, if PWMSYNC = 0 and REINIT = 0 and there is a software trigger event,
then the load of MODH:L and CnVH:L registers is only made at the boundary cycle
(CNTMIN and CNTMAX). In this case, the SWSYNC bit is cleared only at the boundary
cycle, so you do not know when this bit is cleared. Therefore, it is possible a new write to
set SWSYNC happens when FTM is clearing the SWSYNC because it is the selected
boundary cycle of PWM synchronization that was started previously by the software
trigger event.
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
Freescale Semiconductor, Inc.
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