mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 921

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

In 16-bit mode, reading either byte (the MH or ML register) latches the contents of both
bytes into a buffer where they remain latched until the other byte is read. Writing to
either byte (the MH or ML register) latches the value into a buffer. When both bytes have
been written, they are transferred as a coherent value into the SPI match registers.
Addresses: SPI0_ML is FFFF_81A0h base + 7h offset = FFFF_81A7h, SPI1_ML is FFFF_81B0h base + 7h offset = FFFF_81B7h
38.3.9 SPI control register 3 (SPIx_C3)
This register introduces a 64-bit FIFO function on both transmit and receive buffers. It
applies only for an instance of the SPI module that supports the FIFO feature.
FIFO mode is enabled by setting the FIFOMODE bit to 1. A write to this register occurs
only when it sets the FIFOMODE bit to 1.
Using this FIFO feature allows the SPI to provide high speed transfers of large amounts
of data without consuming large amounts of the CPU bandwidth.
Enabling this FIFO function affects the behavior of some of the read/write buffer flags in
the S register as follows:
Freescale Semiconductor, Inc.
• The SPRF of the S register is 1 when the receive FIFO is filled. As a result:
• The SPTEF of the S register is 1 when the transmit FIFO is empty. As a result:
Bits[7:0]
Reset
Field
Read
7–0
Write
• If the RXDMAE bit in the C2 register is 1, SPRF generates a receive DMA
• If the RXDMAE bit in the C2 register is 0 and the SPIE bit in the C1 register is
• If the TXDMAE bit in the C2 register is 1, SPTEF generates a transmit DMA
• If the TXDMAE bit in the C2 register is 0 and the SPTIE bit in the C1 register is
Bit
request.
1, SPRF interrupts the CPU.
request.
1, SPTEF interrupts the CPU.
Hardware compare value (low byte)
7
0
0
6
MCF51JF128 Reference Manual, Rev. 2, 03/2011
SPI0_ML field descriptions
0
5
Preliminary
0
4
Bits[7:0]
Description
0
3
Chapter 38 Serial Peripheral Interface (SPI)
0
2
0
1
0
0
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