mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1163

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

Chapter 44 Integrated Interchip Sound (I2S) / Synchronous Audio Interface (SAI)
The SAI receiver includes a FIFO reset that synchronizes the FIFO read pointer to the
same value as the FIFO write pointer. This empties the FIFO contents and is to be used
after the Receive FIFO Error Flag is set and any remaining data has been read from the
FIFO, and before the Error Flag is cleared. The FIFO Reset is asserted for one cycle only.
44.4.3 Synchronous Modes
The SAI transmitter and receiver can operate synchronously to each other or
synchronously to other SAI peripherals.
44.4.3.1 Synchronous Mode
The SAI transmitter and receiver can be configured to operate with synchronous bit clock
and frame sync.
If the transmitter bit clock and frame sync are to be used by both the transmitter and
receiver, the transmitter should be configured for asynchronous operation and the
receiver for synchronous operation. In synchronous mode, the receiver is only enabled
when both the transmitter and receiver are both enabled. It is recommended that the
transmitter is the last enabled and the first disabled.
If the receiver bit clock and frame sync are to be used by both the transmitter and
receiver, the receiver should be configured for asynchronous operation and the
transmitter for synchronous operation. In synchronous mode, the transmitter is only
enabled when both the receiver and transmitter are both enabled. It is recommended that
the receiver is the last enabled and the first disabled.
When operating in synchronous mode only the bit clock, frame sync and transmitter/
receiver enable are shared. The transmitter and receiver otherwise operate independently,
although configuration registers should be configured consistently across both the
transmitter and receiver.
44.4.3.2 Multiple SAI Synchronous Mode
Synchronous operation between multiple SAI peripherals is not supported on all devices,
and requires the source of the bit clock and frame sync to be configured for asynchronous
operation and the remaining users of the bit clock and frame sync to be configured for
synchronous operation.
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Preliminary
Freescale Semiconductor, Inc.
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