mcf51jf128 Freescale Semiconductor, Inc, mcf51jf128 Datasheet - Page 1277

• Manufacturer Part Number: mcf51jf128
• Description: Mcf51jf128 Reference Manual
• Manufacturer: Freescale Semiconductor, Inc

50.3.9 Program Counter Breakpoint/Mask Registers (PBR0–3,
The PBRn registers define instruction addresses for use as part of the trigger. These
registers’ contents are compared with the processor’s program counter register when the
appropriate valid bit is set (for PBR1–3) and TDR is configured appropriately. PBR0 bits
are masked by setting corresponding PBMR bits (PBMR has no effect on PBR1–3).
Results are compared with the processor’s program counter register, as defined in TDR.
The PC breakpoint registers, PBR1–3, have no masking associated with them, but do
include a valid bit. These registers’ contents are compared with the processor’s program
counter register when TDR is configured appropriately.
The PC breakpoint registers are accessible in supervisor mode using the WDEBUG
instruction and through the BDM port using the WRITE_DREG command using values
shown in BDM Command Set Descriptions.
Freescale Semiconductor, Inc.
L1EPC
L1PCI
L1EA
Field
4–2
1
0
PBMR)
Version 1 ColdFire core devices implement a 24-bit, 16 MB
address map. When programming these registers with a 32-bit
address, the upper byte should be zero-filled when referencing
Enable Level 1 Address Breakpoint
Setting an L1EA bit enables the corresponding address breakpoint. Clearing all three bits disables
the breakpoint.
Bit
20
19
18
Enable Level 1 PC Breakpoint
0
1
Level 1 PC Breakpoint Invert
0
1
Description
Table 50-23. TDR Field Descriptions (continued)
MCF51JF128 Reference Manual, Rev. 2, 03/2011
Description
Address breakpoint inverted. Breakpoint is based outside the range between ABLR
and ABHR.
Address breakpoint range. The breakpoint is based on the inclusive range defined by
ABLR and ABHR.
Address breakpoint low. The breakpoint is based on the address in the ABLR.
Disable
Enable
Do not invert
Invert
Preliminary
NOTE
Chapter 50 Debug
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